Semiconductor OEMs Experience Spending Declines Worldwide

Softening market conditions and rising uncertainty in global trade and economy have impacted semiconductor spending from the world’s top OEMs, currently facing the steepest decline in over a decade. Worldwide spending from semiconductor OEMs will amount to just $316.6 billion in 2019, which is down 7% from 2018.

The recent decline came after two years of double-digit growth, which pushed the served available market (SAM) to its highest level ever at $340.2 billion in 2018. The semiconductor spend market is at an inflection point, where component demand is transitioning from being driven by mobile device manufacturing to being propelled increasingly by industrial and automotive applications.

The weakening semiconductor spend projection for the current year is broadly underpinned by memory IC pricing erosion, along with a number of end-user equipment market demand issues. These include sluggish OEM revenue growth, global economy slowdown, escalating trade tensions, reduced consumer spending, growing surplus of inventory, along with lower growth in major applications such as smartphones and data center servers. Although chip spending from industrial and automotive applications is now quickly on the rise, the combined spending increase remains insufficient to offset overall semiconductor spending market’s decline.

Due to demand saturation in China, North America, and Western Europe, global smartphone shipments are expected to continue their decline throughout 2019. In addition to factors such as longer device replacement cycles, indifference and sluggish device innovation, and consumers biding time for 5G transition, intensified US-China trade and technology tensions are adding excessive burden to the already softened global smartphone market. Apple’s iPhone shipments and market share in China have dropped consistently every quarter since the trade war began.

As the largest buyer of semiconductors, smartphone manufacturers’ decline have significant impact on worldwide semiconductor spending market, with the chip spending contraction value of mobile phones now comprising upwards of 74% of the total $23.7 billion semiconductor spending market decline in 2019. All five top semiconductor OEMs, Apple, Samsung Electronics, Xiaomi, Huawei, and Oppo, will significantly decrease their respective semiconductor purchases during 2019 to respond to these market changes.

Rapid development of cloud based services is driving tremendous demand increase for data center servers over the past several years; however, a demand slowdown in the first half of the year may potentially weigh down on server’s chip spending growth in 2020. This demand has continued to increase as content service providers delay investments due to slow digestion of hyperscale servers and poor macroeconomic conditions in China. Data center servers make up nearly 29% of total DRAM revenue and it’s expected that with the shipments of servers beginning to pick up near the end of the year, the semiconductor spending market will slightly improve and progress strongly into 2020 with robust growth.

 

Recovery in 2020

The semiconductor spending market is expected to rise out of the slump in 2020 as the key semiconductor demand drivers recover and the supply and demand dynamics of memory IC are stabilized. Current forecasts suggest that the semiconductor spending market will recover next year with a 4.5% growth to as much as $331 billion.

Despite new 5G infrastructure and 5G smartphones expected to generate new demand growth for semiconductors, the industry is still only expected to rebound moderately next year as consumer adoption will take some time to meet the pace of production. Once economy of scale finally comes into effect, the devices and network service will become cheaper, further boosting increases to adoption rates of 5G technologies.

With the vast amount of data generated from 5G-related applications, and with the launch of a slew of new 5G services and contents, capital investments in data centers are expected to increase in a move to support and monetize the rapid growth of the 5G service ecosystem. Demand is anticipated to improve significantly for the top server OEMs, thus raising overall data center server semiconductor spending by 13% in 2020, and pushing its overall spending share up to 8.4% from 7.8% during 2019.

Even though the semiconductor market outlook for 2020 appears to be positive with the confidence of 5G emerging as the key growth driver, the risk of further escalation in trade disputes, not just between the US and China, but also Japan and South Korea, will continue to weigh down on the semiconductor market’s recovery and push the manufacturing and semiconductor supply chain industry further into uncertainty. Whether the goal is to relocate or diversify production out of China and into Southeast Asia nations, or to forage for new semiconductor materials sources, the affected parties in the supply chain must rethink and redesign their strategies in order to better manage the risk of being impacted negatively.

In the long unfolding arc of technology innovation, artificial intelligence (AI) looms as immense. In its quest to mimic human behavior, the technology touches energy, agriculture, manufacturing, logistics, healthcare, construction, transportation and nearly every other imaginable industry – a defining role that promises to fast track the fourth Industrial Revolution. And if the industry oracles have it right, AI growth will be nothing shy of explosive.

Internet of Things (IoT) and 4G/5G, both key AI enablers, are expected to account for more than 75 percent of device connections by 2025. In order to process the colossal amount of data central to the promise of AI, from over 30 billion connected devices worldwide, the industry needs to now break through the limits of a key technology: memory.

Memory As A Critical AI Bottleneck

The challenge for memory begins with performance. Historically, every decade, the gains in computer performance have outpaced improvements in memory speed by 100 times, and over the past 20 years that gap has grown. The result of this trend is that memory has bottlenecked computer and AI performance.

The industry has responded by developing several methods to implement memory systems on AI chips, with each being specialized for different performance needs and each requiring different trade-offs. Among the front runners:

  • On-chip memory delivers the highest bandwidth and power efficiency but is limited in capacity.
  • HBM (High Bandwidth Memory) offers both very high memory bandwidth and density.
  • GDDR offers good tradeoffs between bandwidth, power efficiency, cost and reliability.

Since 2012, AI training capability has grown 300,000 times. This growth outpaced Moore’s law by 25,000 times, doubling every 3.5 months, a blistering pace compared to the 18-month doubling cycle of Moore’s law. The staggering recent improvements have been attributed to parallel computing capacity and new application-specific silicon like Google’s Tensor Processing Unit (TPU).

Specialized silicon architectures and parallel engines are one key to sustaining future gains in compute performance and combating the slowing of Moore’s Law and the end of power scaling. By rethinking the way processors are designed for certain markets, chip makers can develop dedicated hardware capable of operating with between 100 and 1,000 times greater energy efficiency than general purpose processors to overcome another big limiter to scaling compute performance: processing power.

For its part, the memory industry can improve performance by signaling at higher data rates and using stacked architectures like HBM for greater energy efficiency and performance, and by bringing compute closer to the data.

Memory scaling for AI

A key challenge is scaling memory for artificial intelligence (AI) applications. Growing consumer demand for better voice, gesture, facial recognition experiences, and more immersive virtual reality and augmented reality interactions rise in importance. Offering these experiences requires more computing capability from high-performance computing (HPC) to make big data analytics possible, to run the analytics themselves, as well as machine learning processes that generate meaningful insights using AI and machine intelligence.

Emerging machine learning applications include classification and security, medicine, advanced driver assistance, human-aided design, real-time analytics, and industrial automation. With 75 billion IoT-connected devices generating data expected by 2025, there will be no shortage of data to analyze. For example, the wings alone on a new Airbus A380-1000 feature over 10,000 sensors. Mountains of this data are stored in massive data centers on magnetic hard drives, then transferred to DRAM before moving to SRAM within the CPU for the hand off to the compute hardware for analysis.

With stored data growing at an exponential clip, the question is how to make sure all other memory systems are able to handle the flood of data. AMD’s answer is a chiplet architecture featuring eight smaller chips around the edge that drive the compute and a large chip in center that doubles the IO interface and memory capability to double chip bandwidth.

AMD has also moved from a legacy GDDR5 memory chip configuration to HBM (high-bandwidth memory) to bring memory bandwidth closer to the GPU to process AI applications more efficiently. The HBM provides much higher bandwidth while reducing power consumption. Compared to DRAM, AMD’s HBM delivers a much faster data rate and far greater memory density than DRAM to put memory closer to the GPU so AI applications are processed more efficiently.

Over the next decade, look for more performance improvements from multi-chip architectures, innovations in memory technology and integration, aggressive 3D stacking and streamlined system-level interconnects. The industry will also continue to drive performance gains in devices, compute density and power through technology scaling.

Although the total volume of data is expected to grow exponentially from proliferating technologies such as 5G, IoT, and autonomous driving applications, magnetic tapes will likely still remain the mainstream data storage medium over the next 10 years. This recent assertion is supported by the idea that magnetic tape storage capacity is expected to grow 30% per year, compared to only 10% for hard disc storage, according to IBM.

At a recent IBM forum in Taipei, the company’s Greater China CTO said that magnetic tapes, after around 50 to 60 years of development, have been a preferred medium to store data mainly because they are cheaper than hard discs and also boast a longer storage life, being able to maintain the security of its data for between 30 and 50 years.

Many data center operators choose magnetic tapes to build their backup data files, but in order to meet different usage needs for cold data and hot data, new storage architectures will need to become available in the future, including a mixed use of flash, tape, and FLAPE (flash + tape).

Data storage industry sources claim that between 70 and 80% of all data stored at data centers are stored with magnetic tapes, although hard discs are increasingly adopted whenever costs permit. Because of this, IBM has developed the Linear Tape Open (LTO) initiative in cooperation with HP and Seagate, and is now the bellwether of magnetic tape technology, which has advanced to LTO-8.

IBM and Sony have also recently teamed up to break the areal density record for the magnetic tape medium, successfully cramming 201 billion bits of uncompressed data into each square inch of tape.

Industry news sources cited Seagate’s estimates that global data volumes will grow from 33ZB in 2017 to over 175ZB by 2025, predicting a growth factor of over 500% within the next eight years.

Intel Showcases New Chip Packaging Powers

Packaging has perhaps never been a hotter subject in popular discourse. Since Moore’s Law no longer seems to provide the impact it once did, another path to better computing is by connecting chips together more tightly within the same package.

At the recent Semicon West event, Intel showcased three new research efforts related to packaging. The first combines two existing technologies to more tightly integrate chiplets, which are smaller chips linked together in a package to form the kind of system that would normally be produced as a single chip. The second effort provides power delivery efficiencies by adding dies at the top of a 3D stack of chips. The final research effort is an improvement on Intel’s chiplet-to-chiplet interface, known as the Advanced Interface Bus (AIB).

The first effort, named “Co-EMIB,” is essentially a way of combining two existing Intel packaging technologies: EMIB (for embedded multidie interconnect bridge) and Foveros. The former bridges two chiplets over a short distance by using a small piece of silicon embedded in a package’s organic substrate. The interconnect lines on silicon can be made narrower than on the organic substrate and can be packed together more tightly to form a high-bandwidth chip-to-chip connection. This method has been used to produce systems like Intel’s Stratix 10 FPGA, which is actually an FPGA chiplet linked to two high-bandwidth DRAM and four high-speed transceiver chiplets in the same package.

Foveros is Intel’s 3D chip-stacking technology. This technology allows die-to-die connections of just 50 micrometers distance, then leading to high-bandwidth vertical connections. Through-silicon vias (or TSVs), conductors that pass vertically through the silicon of the bottom die, then connect the stack to the package substrate.

Combining the two into Co-EMIB lets two or more Foveros stacks communicate through high-density EMIB bridges to build more complex systems. Since connections are only micrometers apart, using an organic substrate that is hard to make perfectly planar, and a fairly large area to pattern, it became quite difficult.

“The scale of it becomes more and more critically [dependent] on how you can hold all your dimensional tolerancing through the assembly process,” says Johanna Swan, a fellow at Intel’s components research and technology development group. “The process tricks become more important in order to manage the size of structures. We’re able to show there’s a path for maintaining that dimensional stability over a larger area.”

The second research effort, Intel’s Omnidirectional Interconnect (ODI), essentially allows for EMIB-like vertical connections. These are larger than typical through-silicon vias, about 70 micrometers across versus an ordinary TSV’s 10 micrometers. Large diameter makes them especially well-suited to deliver power to the top die within a 3D stack. “As you scale that area, you get cleaner, more efficient power delivery,” Swan added.

MDIO, the product of the third effort, should be available in 2020 according to Intel’s Semicon West presentation. It offers 200 gigabytes per second per millimeter of chip edge versus AIB’s 63 GB/s-mm, and it uses 0.50 picojoules per bit versus AIB’s 0.85. Intel compared MDIO to TSMC’s LIPINCON technology, which is also expected in 2020 and delivers 67 GB/s-mm at about the same picojoules per bit.

Intel R&D claims that it will continue to try to increase the number of bumps—the solder ball on/off ramps from a chip— which are available in a given area. Ultimately, getting rid of solder is their primary goal with these research efforts. The intermetallic interface between the solder and the copper interconnects limits current, so chip manufacturers are now exploring a technology known as “hybrid bonding,” which uses a dielectric material and heat to connect one chip’s copper pads to another without using solder.

For many years now, transistors on our microchips have gotten smaller, faster, and cheaper over time. Every two years, the number of transistors on commercial chips has doubled — with this phenomenon becoming widely known as “Moore’s Law.” For several years in the recent past, Moore’s Law does not seem to hold true any longer. Miniaturization of chip sets has reached a natural limit, and new problems begin to arise as a length scale of only a few nanometers is approached.

The next big step in miniaturization may become possible using so-called “two-dimensional (2-D) materials” that consist of only a single atomic layer. With help from a new insulator made from calcium fluoride, scientists at TU Wien (in Vienna, Austria) have created an ultra-thin transistor, which has excellent electrical properties and, in contrast to legacy technologies, can be miniaturized to an even smaller size than previously possible. The new technology was recently presented in the journal Nature Electronics.

 

Ultra-Thin Semiconductors and Insulators

Research surrounding semiconductor materials required to fabricate transistors has shown significant progress in recent years. Ultra-thin semiconductors can now be made from 2-D materials, which consist of just a few atomic layers. “But this is not enough to build an extremely small transistor,” according to Professor Tibor Grasser of the Institute of Microelectronics at TU Wien. “In addition to the ultra-thin semiconductor, we also need an ultra-thin insulator.” This is a result of the fundamental structure of a transistor: the current is able to flow from one side of the transistor to the other, but only as voltage is applied to the middle, which is what creates the electric field. The electrode that provides this field must be electrically insulated from the semiconductor itself.

“There have already been transistor experiments with ultra-thin semiconductors, but until now, they were coupled with ordinary insulators,” said Professor Grasser. “There’s not much benefit in reducing the thickness of the semiconductor when it still has to be combined with a thick layer of insulator material. There’s no way of miniaturizing such a transistor any further. Also, at very small length scales the insulator surface turned out to disturb the electronic properties of the semiconductor.”

Yury Illarionov, from Professor Grasser’s team, then tried a novel approach. The researcher incorporated ultra-thin 2-D-materials, not only for the semiconductor part of the transistor, but also for the insulation mechanism. By selecting ultra-thin insulating materials like ionic crystals, the transistor of only a few nanometers size is able to be constructed. The electronic properties are improved because the ionic crystals have a perfectly regular surface, without a single atom protruding from the surface, which might disturb the electric field. “Conventional materials have covalent bonds in the third dimension — atoms that couple to the neighboring materials above and below,” explained Professor Grasser. “This is not the case in 2-D materials and ionic crystals, and so they do not interfere with the electrical properties of the semiconductor.”

 

The Prototype is a World Champion

To produce the new ultra-thin transistor, calcium fluoride was chosen as the primary insulating material. A calcium fluoride layer was also produced at the Ioffe Institute in St. Petersburg, where the author of the publication, Yury Illarionov, is originally from. The transistor itself was manufactured by Professor Thomas Müller’s team at the Institute of Photonics at TU Wien, and later analyzed by a team at the Institute for Microelectronics.

The first prototype surpassed all of their expectations. “For years, we have received quite a number of different transistors to investigate their technical properties — but we have never seen anything like our transistor with the calcium fluoride insulator,” said Professor Grasser. “The prototype with its superior electrical properties outshines all previous models.”

Following their success, the team now wants to find out which combinations of insulators and semiconductors will work together for the best results. It may still be a few more years before the technology is able to be used for commercially available computer chips because the manufacturing processes for the material layers still has to be optimized. 

“In general, however, there is no doubt that transistors made of 2-D materials are a highly interesting option for the future,” says Tibor Grasser. “From a scientific point of view, it is clear that the fluorides we have just tested are currently the best solution for the insulator problem. Now, only a few technical questions remain to be answered.”

This new type of smaller and faster transistor should enable the computer industry to take the next big step. This way, Moore’s law of exponentially increasing computer power may soon return to relevance.

Vinyl resin copolymer products, like those based on vinyl resin polymers, are ubiquitous and wide-ranging in their applications. Practically speaking, the uses and advantages of copolymers are limited only by the variety of materials which can blend with a given copolymer and act as a medium for it. 

These materials and the copolymers with which they’re blended determine the physical properties of the resulting blend or product. Copolymers can change the properties of the material(s) with which they’re mixed to confer advantages like increased tensile strength or flame resistance; or other properties beneficial for almost any physical property desirable for commercial or industrial purposes, like coating, sealing or adhesion. Virtually any industry which employs chemical engineering can benefit from using copolymer resins.

Industry applications expand and benefit from copolymer technological solutions like, for example, the manufacture of copolymer emulsions without the need for an added emulsifier. Shin-Etsu and its subsidiaries are, by design, at the cutting-edge of such technologies and those like them.

Two product lines resulting from Shin-Etsu’s approach to vinyl resin copolymer technologies are Solbin and Vinyblan. The versatile nature of vinyl resin copolymers allows for considerable variation, even within the same product range. Vinyblan 278, for example, offers greater flexibility than other Vinyblan formulations for coatings, inks and paintings, even though Vinyblan generally excels in these applications anyway.

These are good examples for illustrating how the same copolymer technology can be reformulated and applied in completely different ways. After all, these are only a couple of applications of vinyl resin copolymers among many thousands of other actual applications and frankly innumerable potential applications.

Vinyl resin copolymers have the potential to completely change both materials themselves and materials technology over time. Chemical engineering and the passage of time have yet to exhaust this potential. It will drive industrial solutions for years to come. In the story of vinyl resin copolymers, we’re much closer to the beginning than we are to the end of the technological solutions arising from their application.

Semiconductor fabrication can be well-described as an all-or-nothing industry. This explains the astronomical investments which manufacturers make in technologies and materials. Every stage in the production of a semiconductor requires precision and quality assurance.

Precision is required to guide the substrate throughout the production process, from the growth of the crystalline silicon to the finished product. Steps like etching and lithography require extremely accurate tools and, except insofar as they are becoming automated, highly-skilled human labor and oversight. As the slightest mistake is total failure for semiconductor applications, precision in the highest degree is of the utmost importance.

Likewise, the high quality or purity of materials is just as important. Quality materials are the starting-point of the entire production chain and the purity of those materials used for photomasks, photoresists, thermal management, packaging and the silicon substrate for the wafers themselves must be necessarily beyond reproach (doping aside) or else failure is guaranteed. Semiconductor fabrication begins with the highest quality materials.

Silicon semiconductor substrate is synthetically grown from seed in cylindrical, crystalline ingots. These are then sliced into thin wafers capable of supporting integrated circuits (ICs). The cylinders vary in the diameter of their perpendicular cross-sectional area, yielding wafers of that same diameter. In the semiconductor fabrication industry, the largest universally accepted diameter for silicon wafers is 300mm, although there has been a big push in the semiconductor fabrication industry to move the standard ceiling to 450mm. It remains to be seen exactly how cost-effective 450mm wafers will be.

For the purposes of producing a fully functioning die, flaws and unwanted impurities can ruin the section of silicon wafer in which they’re located. In fact, this is another business-facing factor which has driven Moore’s Law over the decades, since smaller dice sets a higher die per wafer (DPW) ratio. This means that each wafer is more sub-divided and that, as a consequence, each defect disqualifies a smaller area of the wafer than it otherwise would; and therefore less of the overall mass of the wafer has to be discarded for any single flaw. The development of the new 10nm standard for transistors in 2018 now allows an even greater subdivision of the silicon substrate wafer and so proportionately even less waste.

Regardless of the degree of subdivision, higher quality silicon allows fewer flaws in absolute terms. These two factors of die size and silicon quality synergize to optimize the worth of a given ingot. The quality of the ingot determines the viable dice yielded, regardless of the degree of subdivision, and conversely the number of viable dice determines the return on investment.

Together, smaller dice and higher quality silicon minimize waste and maximize return. This is a crucial factor in the semiconductor business, given that the dice first have to pay for the high cost of growing the silicon ingots which yield them in the first place before any profits can be counted. It also affects the cost of production per die, which for consumer electronics ultimately affects the prices paid by end-user as well. 

Moreover, packaging a successful die depends also on the quality of other applied materials. This continues to apply once the die is used in a device and requires careful consideration of materials used in applications like molding, solder and thermal interface. For example, the use of high-grade silicones and epoxies protect otherwise vulnerable circuitry and increase the reliability and longevity of both the die itself and the larger device containing it. So, successful performance by semiconductors at market is therefore governed by the same principal concern found at the very beginning of the manufacturing process: namely, materials of the highest quality.

New and groundbreaking semiconductor technology is now emerging, with exciting implications for applications, quality and cost. The life of the semiconductor begins and ends with the quality of its construction. A better grade of materials mean better semiconductors and a better electronics industry. The use of higher quality materials means less waste, higher profits for manufacturers, lower costs for customers and a longer reliable lifetime for electronics of all kinds.

Vinyls are a simple chemical group, yet they are industrially indispensable. They have some of the broadest practical applications in solution-oriented chemical engineering. In the form of vinyl resin polymers or copolymers, they have the potential to be utilized for an almost limitless set of purposes. For this reason, products derived from these vinyl resins are ubiquitous.

Vinyl resin polymers are the most commercially-visible vinyl resin solutions used. These include polyvinyl acetate (PVAc) and polyvinyl chloride (PVC). Polymerized in water, polyvinyl acetate (PVAc), is an emulsion with widely useful physical qualities which allow for all sorts of coating and adhesive solutions. The most obvious of these is PVA glue, also known as Elmer’s glue, but its full range of applications varies considerably.

More varied still in application is polyvinyl chloride (PVC). Produced globally in immense quantities, PVC is the most popular vinyl resin polymer and the world’s second biggest selling plastic today. A considerable contributing factor in this is almost certainly a financial one of cost-effectiveness. Synthesized from ethylene and chlorine, PVC is one of the most easy plastics to produce. It’s also less susceptible to changing prices of oil, since its chemical composition isn’t exclusively based on hydrocarbons, but includes chlorine as well.

Logistically, polyvinyl chloride is convenient for the production of commodities with a small cost to large benefit ratio. Besides this, PVC’s preeminent properties of strength, durability, corrosion-resistance and lightness have guaranteed its salience in chemical engineering as applied to industrial scale production. Its low cost make it an economical choice for many manufacturers. Accordingly, PVC resin has become, both economically and literally, the very substance of markets like glazing, cladding, facing, plumbing and drainage, as well as the production of consumer-facing food and drink containers, to say nothing of many thousands of other applications.

The largest producer of PVC in the United States is Shintech which, as a subsidiary of Shin-Etsu, is a sister company of MicroSi. Globally, Shin-Etsu itself is the largest single producer, providing roughly 30% of the world’s supply of PVC. In 2018, Shintech announced another expansion of its PVC production, with plans for an additional production facility in the near future. Other major producers of PVC are making similar plans.

The outlook is similar for vinyl resin polymers in general. The market for vinyl resin products grows reliably year on year. This will only continue as producers across the globe expand their production capabilities and entire industries grow up around the demand for products derived from vinyl resins. In the United States, the major producers of these vinyl resins are planning for more of the same — a future where their vinyl polymer products have more applications than ever before.

Today, Intel recognized 35 suppliers for their exceptional commitment to quality in 2018. The suppliers have collaborated with Intel to implement innovative process improvements and serve with the highest level of integrity, while providing superior products and services. Intel has three levels of supplier recognition: the Supplier Continuous Quality Improvement (SCQI) award, the Preferred Quality Supplier (PQS) award and the Supplier Achievement Award (SAA).

The PQS award recognizes suppliers who relentlessly pursue excellence and conduct business with resolute professionalism. To qualify for PQS status, suppliers must exceed high expectations and uncompromising performance goals while scoring at least 80 percent on an integrated report card that assesses performance throughout the year. Suppliers must also achieve 80 percent or greater on a challenging continuous improvement plan and demonstrate solid quality and business systems.

“Companies receiving this year’s Intel Preferred Quality Suppliers award have demonstrated excellence in customer satisfaction and have been critical in enabling our technology and manufacturing roadmaps,” said Mike Mayberry, senior vice president and general manager of Technology Development at Intel. “These suppliers play a crucial role in our relentless pursuit of Moore’s Law as we collaborate to deliver the technology foundation for the future of computing.”

  • Shin Etsu Chemical Co., Ltd.*: silicon wafers, mask blanks, thermal insulating materials, underfill and photoresist

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The distribution partnership covers the territory of New England, New York, New Jersey, Pennsylvania, Virginia and parts of Ohio.

JNS-Smithchem announced its appointment as distributor representing Shin-Etsu MicroSi vinyl resin technology, a division of Nissin Chemical Co. Ltd.

This includes the Solbin vinyl chloride-vinyl acetate copolymers for solvent-based inks and coatings, Vinyblan water-based vinyl chloride, vinyl acetate and acrylic acid ester copolymers, and Chaline silicone acrylic hybrid resins.

“Shin-Etsu MicroSi has very unique water-based technology for the inkjet and specialty coatings markets,” states Bob Whiteley, EVP, JNS-SmithChem. “Their proprietary silicone acrylic hybrid polymers have applications for rubber and plastics, and their solvent-based vinyl copolymer resins continue to be used in specialty coatings ink applications for film and foil where performance is needed.”

“JNS-Smithchem has a strong presence in the coatings market, and their people understand specialty materials and how to bring them to market,” added Ed Nichols, marketing manager for Shin-Etsu MicroSi. “We are excited to be working with them especially when it comes to introducing our newer resin technologies.”

The distribution partnership covers the territory of New England, New York, New Jersey, Pennsylvania, Virginia and parts of Ohio.