The chip making industry is looking forward to an era of new and daring technologies. Apple awaits A-series chips, which will manage smaller processes. The 5nm fab begins its trial run in 2019, and 3nm processing is already being developed. Experts expect the path towards these new technologies to be a straight and uncluttered one. The small scale engineers must work with certainly makes this a challenge, but the solutions aren’t entirely new—old printing and patterning techniques will be applied to this problem.
Scaling: A Growing Process
To achieve the necessary scaling, RC delay will need to be removed from its bottleneck. Transistors and chips must pack more circuits into less space than ever before without adding to the resistance of metal wiring. There is plenty of technology on the market for achieving this today, but the right approach hasn’t been discovered yet. The ultimate technology will need to be both economical and manufacturable: two problems with their own difficulties.
3D NAND has scaled to a maximum of 48 layers, but Rick Gottscho believes 256 layers are possible. Lam has sensors that can generate gigabytes of data from each wafer, an achievement it hopes to improve upon soon. Size isn’t sufficient as a goal, though. The point of scaling is to improve on cost and speed. Smaller devices carry the risk of insufficient charge and leakage. Vertical scaling that extends 3D NAND while simultaneously improving on layer uniformity could mean greater things for tomorrow’s semiconductors.
1 x 1y DRAM technologies were first licensed in 2015. 3D XPoint has evolved beyond it, offering non-volatile memory and a faster, denser architecture that others are trying to improve upon. Many of the problems facing today’s engineers have never been solved before, but 3D logic integration and stacking is quickly pushing the industry forward.