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Intel Showcases New Chip Packaging Powers

Intel Showcases New Chip Packaging Powers

Packaging has perhaps never been a hotter subject in popular discourse. Since Moore’s Law no longer seems to provide the impact it once did, another path to better computing is by connecting chips together more tightly within the same package.

At the recent Semicon West event, Intel showcased three new research efforts related to packaging. The first combines two existing technologies to more tightly integrate chiplets, which are smaller chips linked together in a package to form the kind of system that would normally be produced as a single chip. The second effort provides power delivery efficiencies by adding dies at the top of a 3D stack of chips. The final research effort is an improvement on Intel’s chiplet-to-chiplet interface, known as the Advanced Interface Bus (AIB).

The first effort, named “Co-EMIB,” is essentially a way of combining two existing Intel packaging technologies: EMIB (for embedded multidie interconnect bridge) and Foveros. The former bridges two chiplets over a short distance by using a small piece of silicon embedded in a package’s organic substrate. The interconnect lines on silicon can be made narrower than on the organic substrate and can be packed together more tightly to form a high-bandwidth chip-to-chip connection. This method has been used to produce systems like Intel’s Stratix 10 FPGA, which is actually an FPGA chiplet linked to two high-bandwidth DRAM and four high-speed transceiver chiplets in the same package.

Foveros is Intel’s 3D chip-stacking technology. This technology allows die-to-die connections of just 50 micrometers distance, then leading to high-bandwidth vertical connections. Through-silicon vias (or TSVs), conductors that pass vertically through the silicon of the bottom die, then connect the stack to the package substrate.

Combining the two into Co-EMIB lets two or more Foveros stacks communicate through high-density EMIB bridges to build more complex systems. Since connections are only micrometers apart, using an organic substrate that is hard to make perfectly planar, and a fairly large area to pattern, it became quite difficult.

“The scale of it becomes more and more critically [dependent] on how you can hold all your dimensional tolerancing through the assembly process,” says Johanna Swan, a fellow at Intel’s components research and technology development group. “The process tricks become more important in order to manage the size of structures. We’re able to show there’s a path for maintaining that dimensional stability over a larger area.”

The second research effort, Intel’s Omnidirectional Interconnect (ODI), essentially allows for EMIB-like vertical connections. These are larger than typical through-silicon vias, about 70 micrometers across versus an ordinary TSV’s 10 micrometers. Large diameter makes them especially well-suited to deliver power to the top die within a 3D stack. “As you scale that area, you get cleaner, more efficient power delivery,” Swan added.

MDIO, the product of the third effort, should be available in 2020 according to Intel’s Semicon West presentation. It offers 200 gigabytes per second per millimeter of chip edge versus AIB’s 63 GB/s-mm, and it uses 0.50 picojoules per bit versus AIB’s 0.85. Intel compared MDIO to TSMC’s LIPINCON technology, which is also expected in 2020 and delivers 67 GB/s-mm at about the same picojoules per bit.

Intel R&D claims that it will continue to try to increase the number of bumps—the solder ball on/off ramps from a chip— which are available in a given area. Ultimately, getting rid of solder is their primary goal with these research efforts. The intermetallic interface between the solder and the copper interconnects limits current, so chip manufacturers are now exploring a technology known as “hybrid bonding,” which uses a dielectric material and heat to connect one chip’s copper pads to another without using solder.