The more power microprocessors manage to put out, the smaller the industry expects them to be. The chip making sector is trying to solve the problem by packing transistors closer together, but that generates heat that damages circuitry. Every millimeter of a chip costs money, increases energy usage, and dulls performance. Chipmakers use the surface area they do in part because it’s more budget-friendly and less risky. Innovative fabrication, techniques and microscopic components are needed to find a balance between efficiency and waste reduction. The trouble is that waste means different things to different scientists.
The Problem with Size
Suppliers understandably want to focus on optimization rather than waste because those who are working with massive budgets don’t have the luxury play loosely with risk. The IoT industry is growing at an exponential pace, so manufacturers have little time to go to market with their innovations.
Achieving Size Goals
Most of today’s microprocessors manage a distance of 90 nanometers at their smallest, but there are now products that manage 22 nanometers—the size of a tiny cluster of atoms. This can be achieved by adding materials to chips one atom at a time with precise layering technology. Excellent insulators contribute to better control and require a layer that’s only four atoms deep.
Optimized configuration tends to lead to overwrought expenses, and the process itself is challenging. Even so, the industry can and must configure IPs in a way that satisfies demand. In doing so, they’ll reduce waste automatically, so the benefits are well worthwhile.
Size isn’t always synonymous with wastage. Sometimes, it’s a security feature that prevents other problems. Focusing on shrinking chip sizes as far as possible can interfere with efficiency and risk reduction. Aiming instead for rightsizing has a better chance of success.