Semiconductor Packaging News – Can Copper Revolutionize Interconnects Again?

Over the last few decades, manufacturing processes have driven circuit structure design by increasingly restrictive process kits that have forced designers to accommodate circuit structures to the manufacturing process.  Interconnects in an integrated circuit are becoming the dominant factor in system performance and power dissipation.

The transition from aluminum to copper began in the late 80’s and required significant developments in fabrication techniques which included radically different methods for patterning the metal along with the introduction of barrier metal layers to isolate the silicon from potentially damaging copper atoms.

Benefits of Copper

The most important benefit of copper in integrated circuits is that copper offers lower resistance than aluminum, which had been the dominant interconnect material.  Using a lower resistance interconnect like copper decreases the RC delay which in turn increases the IC speed.  The intrinsic speed limit of an integrated circuit is determined by the frequency at which its transistors can be turned on and off.  Smaller transistors have inherently higher clock frequencies hence advances in IC speed have usually been achieved by down scaling feature sizes.  Currently the speed limit of advanced ICs is set by the delay in signal.

Switching to copper interconnects became a priority in the late 1980’s as feature sizes decreased.  The introduction of copper brought a shift to inlaid metal because copper is very difficult to etch, with non-passivating, non-volatile etch by-products.

At the end of the 1990’s, metal 1 copper lines in Intel’s quarter-micron logic process were 480nm thick.  Now as manufactures consider options for sub-10nm technology nodes, line thickness for critical layers is dropping into the 50-nm range.  Thinner layers mean less material to remove, and a potentially less challenging etch process.

At this year’s IEEE Interconnectivity Conference, researchers, while not disclosing details regarding their etch and clean processes, reported only a thin layer of CuO remaining on the copper surface.

Preliminary electromigration and resistivity results were encouraging.  IMEC’s program director for nano interconnects, Zsolt Tőkei, stated that resistivity in particular was 15% better than comparable damascene structures.  Etched copper lines, as a way of addressing resistivity and electromigration problems, do not introduce new materials into the interconnect stack.

If obstacles to incorporating etched copper lines for the N5 technology node can be overcome, the implications are significant for both the dielectric and metal components of the interconnect stack.  Etched copper lines could prove to be the biggest change to the interconnect stack since copper itself.

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