Move over, 16nm – here comes 10nm chips
Taiwan Semiconductor Manufacturing Company, Limited (TSMC) also known as Taiwan Semiconductor and its long time partners ARM Holdings Plc (ARM) and Synopsys announced recently that they are now able to help manufacturers design chips with 10-nanometer features.
According to Willy Chen TSMC deputy director of design, “The N10 design ecosystem is ready for customer design starts.” He further noted that TSMC and Synopsys have been collaborating for fifteen years and that ARM and TSMC together offer “the most advanced ARM processor cores in the most advanced TSMC technology.”
Now, says Rob Aitken of ARM, “10-nanometer enablement needs an ecosystem,” which the three companies are prepared to provide. He also intimated that “some cool things are under development to make chip design faster”, but he did not elaborate on what they are.
The 10 nanometer node is the technology node following the 14 nm node, and 10 nm class means chips made using process technologies between 10 and 20 nanometer.
The greatest impact of this announcement falls on the semi-conductor designers. Their job of creating circuitry and layout that comply with the fab / foundry design rules becomes more challenging node over node as new and more complex design rules are introduced. But at 20 nm and below, it has become dramatically more difficult.
TSMCs introduction of multi-patterning at 10 nm means new ways of making and verifying coloring assignments. This means creating test layouts and DRC/MP decks, then undertaking process exploration to determine what patterns/structures can be manufactured with what design rules. This exploration is an iterative process in which the foundries continually refine the layout decks and design rules, based on test results
Critical to success is partnering with a supplier and fab / foundry like ARM and TSMC early to understand the design methodology changes and flow changes brought about by designing to 10nm.
The 10-nm node will face even more exciting challenges. If early indications are correct, it brings us back to the 30% + node-over-node increase in DRC checks that we have been dealing with since the 40nm node. At 20nm, some double patterning layout coloring was supported/required. At 10 nm, designers can expect to see significantly more requirements to color layouts before tapeout.
All in all, while a lot is being said about designing with 10 nm, using 20- and 16/14-nm process nodes to become acquainted with the expanding complexity and new manufacturing requirements of advanced nodes will help designers to design using 10 nm with confidence.